Agudais a place and route tool of Shenzhen Giga Design Automation Co., Ltd. and is the only EDA tool designed in China that can provide a complete software solutions for the physical design of digital integrated circuits. It covers the whole electronic design process from Netlist-in to GDS-out, includes a floorplanner, pre-route, an optimizer, a clock-tree synthesizer, a clock tree optimizer, a detail router, and a top-level integrator.
• a full-featured modular P&R tool with a powerful embedded analysis engine that delivers implementation and optimization at every technical point in the P&R for optimal physical design results; supports standard input and output data formats such as Verilog, SDC, LEF/DEF, Standard Cell Library, GDSII file.
• a complete hierarchical top-level design tool, sharing the same timing, place and route engine in chip-level floorplanning and top-level integration, on the basis of providing optimal timing consistency, but also provides a seamless digital design integration environment for complex chip projects;
• Exclusive centric P&R architecture, and unified database structure across the whole design phase, to achieve 2X faster chip design;
• Boosts the performance by 25%, as well as, cut down power consumption by 15% and reduce chip area by 10%, thanks to the patented technology;
• Modern software engineering, fully multithread and distributed programming support for quick and easy design;
• User-friendly interfaces and scripts support, let user to import and deploy Giga’s physical implementation solutions into their existing processes;
• Supports standard input and output formats, excellent timing and power correlation between Aguda and Signoff;
• Routing centric P&R architecture – it makes routing layer, routing mode, congestion and pin connection more effective in P&R stage, to reduce iteration number and speed up design closure;
• Adaptive MCMM (Multi-corner Multi-Mode) technology – automatically selects the worst timing sign-off scenario during optimization, tremendously reduce ECO iteration number after routing stage;
• Highly consistent sign-off timing analysis – embedded timing analysis engine provides excellent timing correlation with STA tool, all optimizations are based on the best final QoR:
◇ supports a variety of on-chip variation models, such as AOCV, SBOCV, SOCV and LVF, etc.
◇ Graph-Based Analysis (GBA) Analysis and Path-Based Analysis (PBA) driven optimization;
◇ Advanced signal integrity and noise analysis;
• Color-Aware DPT routing technology – innovative Color-Aware routing technology to guarantee DPT (Double-Pattern-Technology) design following multiple coloring routing rule at advanced process nodes;
• In-Hierarchy-Optimization- iHO optimization technique that fix boundary violation path at top-level and inside module simultaneously，do not need re-timing or flatten the whole design, significantly reduces memory consumption and reduce top-level design cycle from few weeks to few days;
• Low-resistance (Low-R) routing technology for congestion prediction – accurately estimate congestion and timing at placement optimization stage, leaves top level low-resistance metals for key path routing to optimize timing and improve performance;
• All-in-one clock/data optimization technique – concurrent clock and data optimization to improve performance and reduce power consumption in MCMM scenario; supports a variety of clock trees, such as H-tree, multipoint tree, and grid tree;
• IR drop and EM prediction routing technology – automatically detects and mitigates potential IR drop at the P&R stage, supports EM rules for advanced process nodes to auto detect and repair during routing;
• Low-power driven optimization – supports low-power constraint files in UPF and CPF formats, concurrent optimize static and dynamic power consumption;
• Supports a wide range of process nodes – supports mainly used and advanced processes of multiple semiconductor manufacturers;